RISC-V: Why it could be the future of privacy

Last week, I attended Hong Kong RISC-V Day, a conference that aimed to bring together international experts to discuss the current state and future of computing through RISC-V architecture, with one of the focuses being security and privacy protections.

RISC-V, pronounced “risk five,” stands for reduced instruction set computing (RISC), with the “V” representing the fifth version. An instruction set architecture defines the interface between software and hardware, dictating how a processor executes instructions. The open nature of RISC-V is one of its most significant strengths. It’s an alternative to the x86_64 architecture used by Intel and AMD, or the aarch64 architecture created by ARM. You might not recognize the architecture names, but you probably recognize the companies that created and use them.

While ExpressVPN does not have immediate plans to integrate RISC-V into our production environment, we believe the architecture has immense potential for the future. We’re actively supporting RISC-V at this early stage, including sponsoring the wolfSSL cryptographic library—which we use for our own VPN protocol, Lightway—to add support for hardware acceleration on this architecture. This is important as without it, applications running on RISC-V will suffer from poor performing cryptography.

At the event in Hong Kong, I shared my perspective on RISC-V’s potential to revolutionize hardware in much the same way open source has transformed software. Although RISC-V isn’t yet ready for widespread adoption, it’s advancing faster than any other architecture, and we’re excited to be part of that journey.

The power of hardware acceleration

I also received a DC Roma II laptop powered by the Spacemit K1 SoC, a cutting-edge chip that exemplifies the rapid advancements in RISC-V technology. On this new laptop, we conducted cryptographic benchmarks comparing unaccelerated and hardware-accelerated performance with wolfSSL, and the results were striking.

For ChaCha-Poly1305, with hardware acceleration enabled, the throughput increased from 55.674 MiB/s to 73.745 MiB/s—a 32% improvement. This is crucial for protocols like Lightway, which can leverage ChaCha-Poly1305 for its balance of speed and security.

The most dramatic improvement was observed with AES-256-GCM. On the unaccelerated version, AES-256-GCM achieved only 0.595 MiB/s for both encryption and decryption. However, with hardware acceleration enabled, speeds jumped to 20.723 MiB/s and 20.739 MiB/s, respectively—an astounding 34x increase.

These performance enhancements are significant and have implications not only for VPN protocols like Lightway (which can use either ChaCha or AES-256) but also for any application performing cryptographic operations on RISC-V. This includes critical sectors like IoT devices, automotive systems, and other areas where security and efficiency are paramount.

The road ahead

While these performance gains are impressive, it’s important to keep in mind that RISC-V, especially in the consumer space, isn’t ready for prime time just yet. 

At ExpressVPN, we see RISC-V as a key technology for the future and enthusiastically support its development, recognizing that its production-readiness is still on the horizon. By engaging early, we put ourselves in a strong position to take advantage of this fast-evolving architecture when it becomes more mature.

Stay tuned as we continue to explore and support pioneering technologies like RISC-V. The future of privacy and security is moving fast, and ExpressVPN is committed to being at the forefront of these advancements.